The present invention relates to an information processing apparatus and, more particularly, to an information processing apparatus for performing control of a vector store instruction used in vector processing.
A conventional information processing apparatus will be described below with reference to FIG. 2. Referring to FIG. 2, this conventional information processing apparatus comprises an instruction register 11 for storing instructions, a decoding/checking circuit 12 for decoding an instruction from the register 11. It also comprises a resource managing means 13 for monitoring the use state of a vector register having data to be stored and acknowledging to the decoding/checking circuit 12 that the vector register is readable, when the decoded instruction is determined to be a vector store instruction.
On the basis of the acknowledgement from the resource managing means 13, the decoding/checking circuit 12 sends a vector store instruction execution designation signal to a line 53. A memory control unit 3 has a buffer 32 connected to a memory unit 4 and a path 6 for connecting the buffer 32 to an arithmetic operation executing unit 2.
In response to the vector store instruction execution designation signal, a buffer managing means 31 and a path managing means 33 in the control unit 3 check the use state of the buffer 32 and of the path 6. When the buffer 32 and the path 6 are set in a data transfer enable state, the memory control unit 3 sends a data transfer designation signal to the arithmetic operation executing unit 2 through a line 7. In response to this data transfer designation signal, the arithmetic operation executing unit 2 starts transferring elements to be stored from the vector register to the buffer 32.
When this data transfer is finished, the memory control unit 3 sends a resource release designation signal to the resource managing means 13 through a line 8. This resource release designation signal indicates the end of use of the stored vector register.
Practical instructions used in an information processing apparatus of this type for executing vector processing will be described in detail with reference to FIG. 3A.
Referring to FIG. 3A,
(1) VADD V2.rarw.V0+V1 is a vector addition instruction, for adding data indicated by the contents of vector registers V0 and V1 in units of elements and storing the sum in a vector register V2.
(2) VST M.rarw.V2 is a vector store instruction, for storing data indicated by the contents of the vector register V2 in the memory unit 4. Vector Register V2 has stored the sum resulting from the vector addition instruction VADD indicated by (1) above.
(3) VMPY V4.rarw.V2*V3 is a vector multiplication instruction, for multiplying data indicated by the contents of vector registers V2 and V3 in units of elements and storing the product in a vector register V4.
An operation of a conventional information processing apparatus using the above instructions will be described below with reference to FIGS. 2 and 3B.
Referring to FIGS. 2 and 3B, when the vector addition (VADD) instruction is stored in the instruction register 11, the resource managing means 13 checks the use states of the vector registers V0 and V1, having data to be read out in accordance with the VADD instruction, and that of the vector register V2, for storing the sum. If the registers are not being used, the decoding/checking circuit 12 sends a VADD instruction execution designation signal to the arithmetic operation executing unit 2, and the resource managing means 13 is informed of the use of the vector registers V0, V1, and V2. The resource managing means 13 sets the registers V0, V1, and V2 in a usable state when a predetermined time period has elapsed.
Subsequently, when the vector store (VST) instruction is supplied to the register 11, the resource managing means 13 checks the use state of the vector register V2 having data to be read out in accordance with the vector store (VST) instruction. When the register V2 becomes usable, the decoding/checking means 12 sends a VST instruction execution designation signal to the arithmetic operation executing unit 2 and the memory control unit 3 through the line 53, and the resource managing means 13 is informed of the use of the vector register V2. At this time, the managing means 13 indicates that the register V2 is being used. In response to the VST instruction execution designation signal, the buffer managing means 31 of the memory control unit 3 checks the use state of the buffer 32, and the path managing means 33 checks the use state of the data path 6.
If the two means 31 and 33 determine that the buffer and the path are in a usable state, a data transfer designation signal is sent to the arithmetic operation executing unit 2 through the line 7. In response to this data transfer designation signal, the arithmetic operation executing unit 2 starts transferring data of the vector register V2 to the buffer 32 when a predetermined time period has elapsed. When the transfer is finished, the memory control unit 3 sends a resource release designation signal to the resource managing means 13 through the line 8. In response to the resource release designation signal, the managing means 13 changes the use state designation of the vector register V2 used in accordance with the vector store (VST) instruction to be "usable".
Subsequently, when the vector multiplication (VMPY) instruction is stored in the instruction register 11, the resource managing means 13 checks the use states of the registers V2, V3, and V4 to be used in accordance with the VMPY instruction. If the registers are in a usable state, the circuit 12 sends a VMPY instruction execution designation signal to the arithmetic operation executing unit 2.
In this information processing apparatus, the memory control unit 3 controls a timing of starting data transfer performed in accordance with the vector store instruction by the arithmetic operation executing unit 2 with respect to a vector register having data to be stored. Since, therefore, a timing at which the memory control unit 3 sends a transfer designation signal to the arithmetic operation executing unit 2 is unknown, the execution designation control unit 1 must check the use state of a vector register having data to be stored and confirm that the resource is usable before sending an execution designation signal.
In addition, a time period of using a vector register in accordance with the vector store instruction is not predetermined from the generation timing of execution designation. If, therefore, an instruction using the same vector register is present after the vector store instruction, this instruction must be issued after the memory control unit 3 sends a resource release designation signal. As a result, the entire processing is delayed before and after the vector store instruction.